1. Field of the Invention
This invention relates to digital circuits and in particular, to a phase locked loop (PLL) clock generator with instantaneous frequency shifting capability.
2. Description of the Related Art
Conventional digital systems, such as a digital computer system, use a system clock to synchronize a number of subsystems or components. A typical digital computer system includes a number of subsystems such as a central processing unit (CPU), a random access memory (RAM) and an input/output (I/O) control circuit for controlling peripheral devices such as printers and floppy drives. A system clock generator, typically located near the CPU, generates a global or master clock signal from which multiple synchronous system clock signals are derived. These system clock signals are provided to their respective subsystems, e.g., to the CPU and to the RAM. The system clock generator also provides a peripheral clock signal for driving the I/O control circuit.
With high frequency CPUs (greater than 10 megahertz), a PLL system clock generator is preferably used. As the clock frequency of digital systems approach about 100 megahertz (MHz), the use of a PLL type clock generator or an equivalent which utilizes feedback from the global system clock becomes mandatory for maintaining reliable subsystem synchronization.
FIG. 1 is block diagram showing a conventional PLL clock generator 100. Clock generator 100 includes a phase locking circuit 110, a first divider 120 and a plurality of output buffers 131, 132, . . . 139. Phase locking circuit 110 includes an input node 111 for receiving a variable reference clock signal RCLK, a second input node 112 for receiving a feedback clock signal FBCLK, and an output node 115 for providing a PLL clock signal PLLCLK. Output node 115 of phase locking circuit 110 is coupled to an input node 121 of a first divider 120. In turn, an output node 125 of first divider 120 provides a global clock signal GCLK to the respective input nodes of output buffers 131, 132, . . . 139.
Phase locking circuit 110 can be one of a number of prior art circuits commonly used for PLLs. Clock generator 100 operates by maintaining reference clock signal RCLK and FBCLK at the same frequency and phase. Phase locking circuit 110 compares feedback clock signal FBCLK to reference clock signal RCLK and adjusts PLL clock signal PLLCLK to compensate for any variations in phase and/or frequency between reference clock RCLK signal and feedback clock signal FBCLK, thereby maintaining PLL clock signal PLLCLK in synchronization with reference clock signal RCLK.
The frequency of global clock signal GCLK of a typical computer system is fairly high and not always suitable for directly driving any I/O control circuitry. As such, the frequency of peripheral clock signal PCLK can be is substantially lower than that of global clock signal GCLK A lower frequency peripheral clock signal PCLK is generated by inserting a second divider 140 between output node 125 of first divider 120 and input node 112 of phase locking circuit 110. Second divider 140 generates peripheral clock signal PCLK for driving the I/O control circuit and provides feedback clock signal FBCLK to phase locking circuit 110. In other words, global clock signal GCLK drives the fast subsystems of the computer system, while the slower peripheral clock signal PCLK drives the I/O control circuit and provides feedback clock signal FBCLK.
With the advent of high speed computer systems, it is increasingly important for the computer system to be able to rapidly, preferably within one clock cycle, reduce the frequency of global clock signal GCLK, i.e., enter a slow mode, whenever optimal performance is not required. Lower power consumption and heat generation are reduced significantly when the computer system is in the slow mode. Similarly, it is important to be able to quickly return global clock signal GCLK to its original high frequency, preferably within one clock cycle, when optimal performance is needed again. When the computer system is a high speed portable system, this need to minimize power consumption is even more crucial because of the desire to extend the operating range of a portable computer system's on-board battery.
One major problem with prior art clock generator 100 is caused by the need for clock generator 100 to change the frequency of reference clock signal RCLK in order to change global clock signal GCLK. Changing the frequency of reference clock signal RCLK results in prior art clock generator 100 requiring a lag time to resynchronize to the new frequency of reference clock signal RCLK before global clock signal GCLK and hence system clock signals SCLK(1), SCLK(2), . . . SCLK(n) are sufficiently stable to be relied upon by the respective subsystems of the computer system. Typically, a lag time period of over 1000 clock cycles is required for clock signals PCLK, SCLK(1), SCLK(2), . . . SCLK(n) to re-stabilize. Note that during these relatively long transition periods, the frequency of system clock signals are indeterminate and cannot be depended on. As such, the computer system is idle while the clock signals PCLK, SCLK(1), SCLK(2), . . . SCLK(n) are stabilizing and is unable to perform any useful functions during these lag periods.